By Stephen Nellis
(Reuters) – Intel Corp
The Santa Clara, California-based company is one of the few remaining in the world that both designs and manufactures its own chips. But its manufacturing operations have become a concern among investors after Intel last month said that its next-generation chip-making process, called its 7-nanonmeter process node, would be delayed.
Analysts believe the delays could cement the lead that rivals such as Taiwan Semiconductor Manufacturing Co <2330.TW> have gained in making smaller, more power efficient chips. Intel’s shares have fallen nearly 20% since the delays were disclosed.
On Thursday, Intel sought to buck the notion that the single-number names given to each generation of chip process node tell the entire story by disclosing improvements on its existing 10-nanonmeter process node. It announced a new way of making what it now calls “SuperFin” transistors, which, along with a new material being used to improve the capacitors on chips, is expected to boost the performance of Intel’s forthcoming processors, despite their still being made on 10-nanonmeter manufacturing lines.
“It is 20%, the largest intra-node jump ever in our history,” Raja Koduri, Intel’s chief architect, said of the performance gain in an interview with Reuters. “It’s actually same as what you would get with one full Moore’s Law node of performance.”
It will not be possible to test those claims in the real world until Intel’s new chips come out, but its “Tiger Lake” laptop chips slated for release this fall will use the chips.
Even with the new transistor technology, Koduri said Intel has re-worked its chip design process to be able to more easily use either its own chip factories or outside chip factories, whichever is needed to create the best chips.
“Whatever gets us to deliver those products on time, with leadership performance, we have the flexibility and are going to utilize that,” he said.
(Reporting by Stephen Nellis in San Francisco; Editing by Leslie Adler)
